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IDT5T929 PRECISION CLOCK GENERATOR OC-48 APPLICATIONS
INDUSTRIAL TEMPERATURE RANGE
PRECISION CLOCK GENERATOR OC-48 APPLICATIONS
FEATURES: DESCRIPTION:
IDT5T929
* Input frequency: - For SONET non-FEC: 19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz, 311.04MHz, or 622.08MHz - For SONET FEC: 20.83MHz, 41.66MHz, 83.31MHz, 166.63MHz, 333.26MHz, or 666.52MHz - For 10GE copper: 19.53MHz, 39.06MHz, 78.125MHz, 156.25MHz, 312.5MHz, or 625MHz - For 10GE optical: 20.14MHz, 40.28MHz, 80.56MHz, 161.13MHz, 322.26MHz, or 644.53MHz * Output frequency range selection * 1x, 2x, 4x, 8x, 16x, and 32x outputs on QOUT * Regenerated input clock on QREG * Lock indicator * Power-down mode * LVPECL or LVDS outputs * Two modes of output frequency range - Mode 0: QOUT range 155.5 - 166.6MHz. QREG is a regenerated version of the input clock. - Mode 1: QOUT range 622 - 666.5MHz. QREG is a regenerated version of the input clock frequency. * Hitless switchover * Differential LVPECL, LVDS, or single-ended LVTTL input interface * 2.375 - 3.465V core and I/O * Available in VFQFPN package
The IDT5T929 generates a high precision FEC (Forward Error Correction) or non-FEC source clock for SONET/SDH systems as well as a source clock for Gigabit Ethernet systems. This device also has clock regeneration capability: it creates a "clean" version of the clock input by using the internal oscillator to square the input clock's rising and falling edges and remove jitter. In the event that the main clock input fails, the device automatically locks to a backup reference clock using a hitless switchover mechanism. This device detects loss of valid CLKIN and leaves the VCO of the PLL at the last valid frequency while an alternate input REFIN is selected. If CLKIN and REFIN are different frequencies, the multiplication factor will be adjusted to retain the same output frequency. The IDT5T929 can act as a translator from a differential LVPECL, LVDS, or single-ended LVTTL input to LVPECL or LVDS outputs. The IDT5T929-10 has LVDS outputs and the IDT5T929-30 has LVPECL outputs. The two modes of output frequency range are controlled by the SELmode. When SELmode is high or low, the QOUT is a multiplied version of the input clock while QREG is a regenerated version of the input clock.
APPLICATIONS:
* * * * *
Terabit routers Gigabit ethernet systems SONET / SDH systems Digital cross connects Optical transceiver modules
FUNCTIONAL BLOCK DIAGRAM
CLKIN CLKIN
INPUT MUX
QREG PLL DIVN QREG
QOUT DIVM QOUT
REFIN REFIN
LOCK, FREQ. DETECTOR
CONTROL LOGIC PD SELMODE
LOCK
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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c 2004 Integrated Device Technology, Inc.
JANUARY 2004
DSC 6400/13
IDT5T929 PRECISION CLOCK GENERATOR OC-48 APPLICATIONS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
QOUT QOUT GND GND VDD VDD PD
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDD VI VO
21 20 19 VDD GND QREG QREG GND VDD LOCK
Description Power Supply Voltage Input Voltage Output Voltage Junction Temperature Storage Temperature
Max -0.5 to +4.1 -0.5 to +4.1 -0.5 to VDD+0.5 150 -65 to +165
Unit V V V C C
28 GND CLKIN CLKIN GND REFIN REFIN GND 1 2 3 4 5 6 7 8
27
26
25
24
23
22
TJ TSTG
GND
18 17 16 15
NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
9
10
11
12
13
14
CAPACITANCE(TA = +25C, f = 1MHz, VIN = 0V)
Parameter CIN COUT Description Input Capacitance Output Capacitance Typ. 2.5 -- Max. 3 -- Unit pF pF
TEST
TEST
VDD
VDD
SELMODE
VDD
GND
VFQFPN TOP VIEW
NOTE: 1. Capacitance applies to all inputs except SELmode.
RECOMMENDED OPERATING RANGE
Symbol TA VDD VT Description Ambient Operating Temperature Power Supply Voltage Termination Voltage (LVPECL) Termination Voltage (LVDS) Min. -40 2.375 -- -- Typ. +25 -- VDD - 2 1.2 Max. +85 3.465 -- -- Unit C V V
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IDT5T929 PRECISION CLOCK GENERATOR OC-48 APPLICATIONS
INDUSTRIAL TEMPERATURE RANGE
INPUT FREQUENCY RANGE(1)
19.4MHz - 20.9MHz 38.8MHz - 41.7MHz 77.7MHz - 83.4MHz 155.5MHz - 167MHz 311MHz - 334MHz 622MHz - 667MHz
NOTE: 1. The PLL will automatically detect the input frequency and adjust the multiply ratio to generate the appropriate output frequency.
LOCK FREQUENCY DETECTOR
The 5T929 will lock to, and track, a valid CLKIN signal; LOCK will be low when this has occurred. If CLKIN fails, the 5T929 PLL will smoothly switch to lock to REFIN without generating any glitches on the output. The fact that the PLL is locked to REFIN rather than CLKIN is indicated by a high state on LOCK. When a valid input is then applied to CLKIN, the 5T929 will smoothly switch back to locking on CLKIN, and LOCK will go low. LOCK will also switch to high should the frequency of CLKIN drift close to the limits of the VCO tuning range.
OUTPUT FREQUENCY RANGE
SELmode L H QOUT/QOUT 155.5 - 166.6 622 - 666.5 QREG/QREG regenerated CLKIN/CLKIN regenerated CLKIN/CLKIN Unit MHz MHz
PIN DESCRIPTION
Pin Name CLKIN, CLKIN I/O I Type Adjustable(1) Description Differential or single-ended clock input signal. For differential, LVPECL or LVDS supported. If left open-circuited, inputs will float to LVTTL threshold voltage so that either input may be used as a single-ended input. A capacitor to ground should be connected on the floating input. Differential reference clock input. The reference clock input is used as an input to the PLL when CLKIN/CLKIN fails. Differential or single-ended clock input signal. For differential, LVPECL or LVDS supported. If left open-circuited, inputs will float to LVTTL threshold voltage so that either input may be used as a single-ended input. A capacitor to ground should be connected on the floating input. 2 level input to select output frequency range for QOUT/QOUT and QREG/QREG (see Output Frequency Range table) Power Down Control. Shuts off entire chip when LOW. Differential clock output. LVPECL or LVDS outputs. Regenerated clock output from CLKIN/CLKIN, LVPECL, or LVDS outputs. LOW when PLL is locked to CLKIN, HIGH in all other conditions Factory testing only. This pin should be left unconnected. No connection PWR PWR Power Supply Ground
(3)
REFIN, REFIN
I
Adjustable(1)
SELmode PD QOUT, QOUT QREG, QREG LOCK TEST NC VDD GND
I I 0 0 0
2-level(2) LVTTL Adjustable(3) Adjustable LVTTL
NOTES: 1. Inputs are capable of translating the following interface standards: Single-ended 3.3V LVTTL levels Single-ended 2.5V LVTTL levels Differential LVPECL levels Differential LVDS levels 2. 2-level inputs are static inputs and must be tied to VDD or GND. 3. Outputs can be LVPECL or LVDS.
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IDT5T929 PRECISION CLOCK GENERATOR OC-48 APPLICATIONS
INDUSTRIAL TEMPERATURE RANGE
CLOCK INPUT/OUTPUT CONFIGURATION DESCRIPTION
Application Non-FEC REFIN (MHz) 19.44, 38.88, 77.76, 155.52, 311.04, 622.08 CKIN (MHz) 19.44 38.88 77.76 155.52 311.04 622.08 FEC 20.83, 41.66, 83.31, 166.63, 333.26, 666.52 20.83 41.66 83.31 166.63 333.26 666.52 10GE copper 19.53, 39.06, 78.12, 156.25, 312.5, 625 19.53 39.06 78.12 156.25 312.5 625 10GE optical 20.14, 40.28, 80.56, 161.13, 322.26, 644.53 20.14 40.28 80.56 161.13 322.26 644.53 SELmode LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH LOW HIGH QREG (MHz) 19.44 19.44 38.88 38.88 77.76 77.76 155.52 155.52 311.04 311.04 622.08 622.08 20.83 20.83 41.66 41.66 83.31 83.31 166.63 166.63 333.26 333.26 666.52 666.52 19.53 19.53 39.06 39.06 78.12 78.12 156.25 156.25 312.50 312.5 625 625 20.14 20.14 40.28 40.28 80.56 80.56 161.13 161.13 322.26 322.26 644.53 644.53 QOUT (MHz) 155.52 622.08 155.52 622.08 155.52 622.08 155.52 622.08 155.52 622.08 155.52 622.08 166.63 666.52 166.63 666.52 166.63 666.52 166.63 666.52 166.63 666.52 166.63 666.52 156.25 625 156.25 625 156.25 625 156.25 625 156.25 625 156.25 625 161.13 644.53 161.13 644.53 161.13 644.53 161.13 644.53 161.13 644.53 161.13 644.53
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IDT5T929 PRECISION CLOCK GENERATOR OC-48 APPLICATIONS
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS(1,2)
Symbol IDD_PD IDD ITOT Parameter Power Supply Current Power Supply Current per Input HIGH (LVTTL inputs only) Total Power Supply Current VDD = Max., QOUT = 622MHz, All outputs unloaded -- 200 mA
NOTES: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations. 2. As a general requirement, these parts must be capable of operating at the maximum frequency under a nominal load at a reasonable operating temperature. That means that these parts must not burn up under extended use in a typical application.
Test Conditions VDD = Max., PD = GND, All outputs unloaded VDD = Max., VIN = 2.375V
Typ. -- --
Max 50 100
Unit A A
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol VIHH VILL I2 Parameter Input HIGH Voltage Level(1) Input LOW Voltage Level(1) 2-Level Input DC Current Test Conditions 2-Level Inputs Only 2-Level Inputs Only VIN = VDD VIN = GND Min. VDD - 0.4 -- -- -200 Max -- 0.4 200 -- Unit V V A
HIGH Level LOW Level
NOTE: 1. These inputs are normally wired to VDD or GND. If these inputs are switched dynamically after powerup, the function and timing of the outputs may be glitched, and the PLL may require additional tAQ time before all datasheet limits are achieved.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVTTL
Symbol IIH IIL VIK VIN VIH VIL Parameter Input HIGH Current Input LOW Current Clamp Diode Voltage DC Input Voltage DC Input HIGH DC Input LOW Test Conditions VDD = 3.465V VDD = 3.465V VDD = 2.375V, IIN = -18mA Min. -- -- -- - 0.3 1.7 -- Typ. -- -- - 0.7 -- -- -- Max 1 1 - 1.2 +3.465 -- 0.7 Unit A V V V V
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVPECL(1)
Symbol IIN VCMR VDIF VOH VOL VSWING Parameter Input Current (CLKIN, REFIN) Common Mode Input Voltage Differential Voltage Required to Toggle Input Output Voltage HIGH (terminated through 50 tied to VDD - 2V)(2) Output Voltage LOW (terminated through 50 tied to VDD - 2V) Peak-to-Peak Output Voltage Swing
(2)
Test Conditions VDD = 3.465V
Min. -20 1 100 VDD - 1.15 VDD - 1.95 0.55
Typ. -- -- -- -- -- --
Max. +20 VDD - 0.3 -- VDD - 0.9 VDD - 1.61 0.93
Unit A V mV V V V
Input Characteristics
Output Characteristics
NOTES: 1. VDD = 2.375 - 3.645V. 2. Not to exceed VDD - 0.05V.
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IDT5T929 PRECISION CLOCK GENERATOR OC-48 APPLICATIONS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVDS
Symbol IIN VCM VDIF VOT(+) VOT(-) VOT VOS VOS IOS IOSD Parameter Input Current (CLKIN, REFIN) Common Mode Input Voltage Range
(1)
Test Conditions VDD = 3.465V
Min. -20 0.9 100 247 -247 -- 1.125 --
Typ. -- -- -- -- -- -- 1.2 -- 9 6
Max. +20 VDD - 0.05 -- 454 -454 50 1.375 50 24 12
Unit A V mV mV mV mV V mV mA mA
Input Characteristics
Differential Voltage Required to Toggle Input Differential Output Voltage for the TRUE Binary State Differential Output Voltage for the FALSE Binary State Change in VOT Between Complementary Output States Output Common Mode Voltage (Offset Voltage) Change in VOS Between Complementary Output States Outputs Short Circuit Current Differential Outputs Short Circuit Current VOUT(+) and VOUT(-) = 0V VOUT(+) = VOUT(-)
Output Characteristics
-- --
NOTE: 1. Not to exceed VDD - 0.05V.
INPUT TIMING REQUIREMENTS
Symbol REFH FREF REFTOL FCLKIN CLKINH tAQ LOCKTOL tJIT(TOL) Parameter Input Reference Clock Duty Cycle Input Reference Clock Range Input Reference Clock Frequency Tolerance Clock in Frequency Range Clock in Duty Cycle Acquisition Time from Return of Valid CLKIN Frequency Tolerance for LOCK Tolerance to Input Jitter Min. 40 19.44 -100 19.44 40 -- -600 Typ. 50 -- -- -- 50 60 450 GR-253 Sect. 5.6.2.2 Max. 60 666.52 100 666.52 60 150 600 Unit % MHz ppm MHz % us ppm
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol QOUT QREG CLKIN tR tF tSK PLLBW tP tJ tDUTY Parameter Multiplied Clock Output Frequency Regenerated Clock Output Frequency Input Clock Frequency Output Rise Time Output Fall Time Skew between QOUT and QREG PLL Bandwidth Jitter Transfer Peaking Output frequency = 622MHz - 666.5MHz Jitter Generation(1) (with 12KHz to 20MHz filter) Output Duty Cycle
NOTE: 1. All input frequencies permitted by PLL bandwidth.
Min. SELmode = LOW SELmode = HIGH 155.52 622.08 19.44 19.44 LVPECL LVDS LVPECL LVDS -- -- -- -- -- 250 -- -- -- -- 45 Output frequency = 155.5MHz - 166.6MHz Output frequency = 77.7MHz - 83.4MHz
Typ. -- -- -- -- 150 100 150 100 10 305 0.05 0.4 0.8 1.2 --
Max. 166.63 666.52 666.52 667 -- -- -- -- 20 500 0.1 1 3.4 3.5 55
Unit MHz MHz MHz ps ps ps KHz dB ps (RMS) %
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IDT5T929 PRECISION CLOCK GENERATOR OC-48 APPLICATIONS
INDUSTRIAL TEMPERATURE RANGE
TEST CONDITIONS
A
LVDS
DRIVER
VDIFF
50 VT TEST POINT 50 B
Test Circuit for LVDS Output Characteristics
A 50
VDIFF
B
VT
50
Test Circuit for LVDS Input Characteristics
A LVPECL DRIVER 50
VDIFF
50 B
Test Circuit for LVPECL Output Characteristics
VDD - 2V
A
VDIFF
B
50
VB
50
VB = VDD - 2V
Test Circuit for LVPECL Input Characteristics 7
IDT5T929 PRECISION CLOCK GENERATOR OC-48 APPLICATIONS
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XXXXX Device Type XX Package X Process
I NL
-40C to +85C (Industrial)
Thermally Enhanced Plastic Very Fine Pitch Quad Flat No Lead Package Precision Clock Generator - LVDS Output Precision Clock Generator - LVPECL Output
5T929-10 5T929-30
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 8
for Tech Support: logichelp@idt.com (408) 654-6459

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